OpenRAM/compiler/pgates
mrg fc85dfe29f Add boundary to all pgates 2020-04-21 15:21:57 -07:00
..
pand2.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pand3.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pbuf.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pdriver.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pgate.py Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
pinv.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pinvbuf.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pnand2.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pnand3.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pnor2.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
precharge.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
ptristate_inv.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
ptx.py Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
pwrite_driver.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
single_level_column_mux.py port_data: Each submodule now specifies their bl/br names 2020-02-12 15:00:50 +01:00