OpenRAM/compiler
mole99 8032fa75a4 Add LEF output for ROM 2023-12-21 08:07:49 +01:00
..
base fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
characterizer Force to use bash for simulators 2023-08-10 16:05:24 -07:00
datasheet Update copyright year 2023-01-28 22:56:27 -08:00
drc Update copyright year 2023-01-28 22:56:27 -08:00
gdsMill Use library imports globally 2022-11-27 13:01:20 -08:00
model_configs Update copyright year 2023-01-28 22:56:27 -08:00
modules Add LEF output for ROM 2023-12-21 08:07:49 +01:00
router Remove unused local variable 2023-12-05 11:18:58 -08:00
tests fixed missing broken stamp 2023-10-31 23:24:21 -07:00
verify workaround for magic drc in gf180 2023-10-31 23:24:21 -07:00
Makefile Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
debug.py Add timestamps to the log file 2023-10-05 14:55:05 -07:00
gen_stimulus.py Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
globals.py Fix typo 2023-09-06 21:38:19 -07:00
model_data_util.py Update copyright year 2023-01-28 22:56:27 -08:00
options.py force multi-delay chain pinouts to be user configurable 2023-09-27 13:15:45 -07:00
rom.py Add LEF output for ROM 2023-12-21 08:07:49 +01:00
rom_config.py ROM binary file support 2023-04-03 16:04:12 -07:00
run_profile.sh
sram.py Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108) 2023-09-03 18:21:31 -07:00
sram_config.py Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
sram_factory.py Update copyright year 2023-01-28 22:56:27 -08:00
view_profile.py Update copyright year 2023-01-28 22:56:27 -08:00