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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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fb6a665514bc38a4b1715d5aa9f06de78bf9308d
OpenRAM/compiler/example_configs
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jcirimel d22164bd48 single port progess
2020-09-14 18:11:38 -07:00
..
big_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_1rw_1r_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_1rw_2mux_scn4m_subm.py
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
example_config_1w_1r_scn4m_subm.py
fix merge conflicts
2020-07-21 11:38:34 -07:00
example_config_freepdk45.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_scn4m_subm.py
revert example scn4m to non netlist only
2020-02-09 23:52:11 -08:00
giant_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
medium_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
run1.py
single port progess
2020-09-14 18:11:38 -07:00
run2.py
single port progess
2020-09-14 18:11:38 -07:00
run3.py
single port progess
2020-09-14 18:11:38 -07:00
run4.py
single port progess
2020-09-14 18:11:38 -07:00
run5.py
single port progess
2020-09-14 18:11:38 -07:00
s8config.py
single port progess
2020-09-14 18:11:38 -07:00
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