Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank ...

for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.

2018-07-13 14:45:46 -07:00

..

contact.py

Fix analytical power of contact with new hierarchy_design level introduced.

2018-07-10 10:17:23 -07:00

design.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

geometry.py

Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.

2018-03-23 08:14:09 -07:00

hierarchy_design.py

Modify unit tests to reset options during init_openram so

2018-07-10 16:39:32 -07:00

hierarchy_layout.py

Getting single bank to work reliably. Removed tri_gate from bank

2018-07-13 14:45:46 -07:00

hierarchy_spice.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

lef.py

Move last few modules to base dir

2018-02-09 10:29:37 -08:00

path.py

Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev

2018-02-09 10:25:28 -08:00

pin_layout.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

route.py

Move last few modules to base dir

2018-02-09 10:29:37 -08:00

utils.py

Move utils to base.

2018-02-09 10:42:23 -08:00

vector.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

verilog.py

Move last few modules to base dir

2018-02-09 10:29:37 -08:00

wire.py

Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev

2018-02-09 10:25:28 -08:00