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base
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Further fixes for new verilog naming convention
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2022-08-18 11:03:13 -07:00 |
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characterizer
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Merge branch 'dev' into multibank
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2022-08-12 21:45:26 -07:00 |
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datasheet
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Remove line ending whitespace
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2022-07-22 19:52:38 +03:00 |
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drc
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Remove line ending whitespace
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2022-07-22 19:52:38 +03:00 |
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gdsMill
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…
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model_configs
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Added shared config which is imported in all model configs. Shared config only hold model type for now.
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2021-09-15 13:00:51 -07:00 |
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modules
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replica code working but failing lvs
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2022-09-07 19:32:25 -07:00 |
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router
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Fix print errors in code format unit test.
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2022-07-26 12:20:15 -07:00 |
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tests
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tests for new capped array module
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2022-09-07 12:39:01 -07:00 |
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verify
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add flatglob to tech file; sky130 replica col lvs working
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2022-08-22 15:30:11 -07:00 |
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Makefile
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Move tests to test Makefile
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2021-11-03 11:36:19 -07:00 |
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debug.py
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Fix print errors in code format unit test.
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2022-07-26 12:20:15 -07:00 |
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gen_stimulus.py
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…
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globals.py
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Merge branch 'dev' into multibank
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2022-08-12 21:45:26 -07:00 |
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model_data_util.py
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Remove line ending whitespace
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2022-07-22 19:52:38 +03:00 |
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openram.py
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Use packages for imports.
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2022-07-13 15:55:57 -07:00 |
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options.py
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Remove experimental power option.
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2022-05-23 10:08:35 -07:00 |
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printGDS.py
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Remove line ending whitespace
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2022-07-22 19:52:38 +03:00 |
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processGDS.py
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Remove line ending whitespace
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2022-07-22 19:52:38 +03:00 |
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run_profile.sh
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…
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sram_factory.py
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Use packages for imports.
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2022-07-13 15:55:57 -07:00 |
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uniquifyGDS.py
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view_profile.py
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…
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