Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

2021-09-07 15:56:27 -07:00

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bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

bitcell_2port.py

Added direction information functions to 2-port bitcell modules

2021-06-21 17:19:15 -07:00

bitcell_base.py

Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

2021-09-07 15:56:27 -07:00

col_cap_bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

col_cap_bitcell_2port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

dummy_bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

dummy_bitcell_2port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

dummy_pbitcell.py

Update copyright year.

2021-01-22 11:23:28 -08:00

pbitcell.py

Update copyright year.

2021-01-22 11:23:28 -08:00

replica_bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

replica_bitcell_2port.py

Added direction information functions to 2-port bitcell modules

2021-06-21 17:19:15 -07:00

replica_pbitcell.py

Update copyright year.

2021-01-22 11:23:28 -08:00

row_cap_bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

row_cap_bitcell_2port.py

Update copyright year.

2021-01-22 11:23:28 -08:00