Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
ebc91814e55ee4501bef7acf3cfa9465c7f9c96e
OpenRAM/compiler/bitcells
T
History
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell.
2021-07-12 14:25:37 -07:00
..
bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
bitcell_2port.py
Added direction information functions to 2-port bitcell modules
2021-06-21 17:19:15 -07:00
bitcell_base.py
Added on resistance functions for pgates, custom cells, and bitcell.
2021-07-12 14:25:37 -07:00
col_cap_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
col_cap_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
dummy_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
dummy_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
dummy_pbitcell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
pbitcell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
replica_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
replica_bitcell_2port.py
Added direction information functions to 2-port bitcell modules
2021-06-21 17:19:15 -07:00
replica_pbitcell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
row_cap_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
row_cap_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
Powered by Gitea Version: 1.27.2 Page: 516ms Template: 12ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API