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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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e5dcf5d5b1340b43376ef93b339015f33df5b785
OpenRAM/technology/scn4m_subm/tech
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Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
2018-10-30 22:19:26 -07:00
..
__init__.py
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
LICENSE.txt
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
SCN4M_SUBM.20.tech
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech.py
Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
2018-10-30 22:19:26 -07:00
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