Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.		2018-10-30 22:19:26 -07:00
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gds_lib	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
mag_lib	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
models	Added scn4m_subm.	2018-09-13 12:53:35 -07:00
sp_lib	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
sue_lib	Added scn4m_subm.	2018-09-13 12:53:35 -07:00
tech	Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.	2018-10-30 22:19:26 -07:00
tf	Supply router working except:	2018-09-18 12:57:39 -07:00