mrg 01a73b31e1 Fix power ring routing boundary bug.

2022-03-18 10:32:25 -07:00

..

and2_dec.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

and3_dec.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

and4_dec.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

bank_select.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

bank.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

bitcell_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

bitcell_base_array.py

replica col lvs fix

2021-12-15 14:19:52 -08:00

col_cap_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

column_mux_array.py

Fix offset to center select signal between bitlines

2022-02-23 15:38:11 -08:00

control_logic.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

delay_chain.py

Fix power ring routing boundary bug.

2022-03-18 10:32:25 -07:00

dff_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

dff_buf_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

dff_buf.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

dff_inv_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

dff_inv.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

dummy_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

global_bitcell_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

hierarchical_decoder.py

Add some vertical/horizontal pins for sky130 only

2022-03-16 07:58:29 -07:00

hierarchical_predecode2x4.py

Skywater changes.

2021-03-22 15:48:14 -07:00

hierarchical_predecode3x8.py

Skywater changes.

2021-03-22 15:48:14 -07:00

hierarchical_predecode4x16.py

Skywater changes.

2021-03-22 15:48:14 -07:00

hierarchical_predecode.py

Power routing changes.

2022-03-06 09:56:00 -08:00

local_bitcell_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

module_type.py

Update copyright year.

2021-01-22 11:23:28 -08:00

multibank.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

orig_bitcell_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

port_address.py

Power routing changes.

2022-03-06 09:56:00 -08:00

port_data.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

precharge_array.py

Add some vertical/horizontal pins for sky130 only

2022-03-16 07:58:29 -07:00

replica_bitcell_array.py

Add some vertical/horizontal pins for sky130 only

2022-03-16 07:58:29 -07:00

replica_column.py

Route horizontal supplies in write driver.

2022-03-01 14:37:51 -08:00

row_cap_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

sense_amp_array.py

Power routing changes.

2022-03-06 09:56:00 -08:00

tri_gate_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00

wordline_buffer_array.py

Build changes.

2022-03-06 10:31:43 -08:00

wordline_driver_array.py

Fix power ring routing boundary bug.

2022-03-18 10:32:25 -07:00

write_driver_array.py

Power routing changes.

2022-03-06 09:56:00 -08:00

write_mask_and_array.py

Remove add_mod and add module whenever calling add_inst.

2021-11-22 11:33:27 -08:00