Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules.

2019-04-24 14:23:22 -07:00

..

contact.py

Added corner information for analytical power estimation.

2019-03-04 19:27:53 -08:00

design.py

Added initial graph for correct naming

2019-04-19 01:27:06 -07:00

geometry.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

hierarchy_design.py

Added graph creation and functions in base class and lower level modules.

2019-04-24 14:23:22 -07:00

hierarchy_layout.py

Return empty set instead of a list.

2019-04-01 15:59:57 -07:00

hierarchy_spice.py

Applied quick corner estimation to analytical delay.

2019-04-09 12:26:54 -07:00

lef.py

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

pin_layout.py

Fix instersection bug. Improve primary and secondary pin algo.

2018-12-04 16:53:04 -08:00

route.py

Convert all contacts to use the sram_factory

2019-01-16 16:56:06 -08:00

utils.py

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

vector.py

…

verilog.py

Remove tabs

2019-01-11 14:16:57 -08:00

wire_path.py

Change path to wire_path for Anaconda package conflict

2019-01-25 15:07:56 -08:00

wire.py

Change path to wire_path for Anaconda package conflict

2019-01-25 15:07:56 -08:00