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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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dfb2cf3cbd5e9308838b478268905b7b32b58447
OpenRAM/compiler/router
T
History
Matt Guthaus dfb2cf3cbd Change analyze_pins to a heuristic algorithm less than O(n^2)
2018-12-07 12:41:32 -08:00
..
tests
Simplifying supply router to single grid track
2018-12-04 08:41:57 -08:00
direction.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_cell.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_path.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_utils.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
grid.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
pin_group.py
Fix instersection bug. Improve primary and secondary pin algo.
2018-12-04 16:53:04 -08:00
router_tech.py
Cleanup code. Add time breakdown for SRAM creation.
2018-12-05 09:51:17 -08:00
router.py
Change analyze_pins to a heuristic algorithm less than O(n^2)
2018-12-07 12:41:32 -08:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Provide more stats in -v output
2018-12-06 14:11:15 -08:00
vector3d.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
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