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OpenRAM/compiler/modules
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Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 		2020-01-28 15:46:14 +01:00
..
bank.py Add separate well design rules. 2020-01-23 19:43:41 +00:00
bank_select.py Supply indexing bug resolved. Recompute width/height basted on insts. 2019-12-19 16:19:21 -08:00
base_array.py Add custom cell properties to technologies 2020-01-28 15:46:14 +01:00
bitcell_array.py Bitcell arrays: Create abstract base class 2020-01-28 10:59:58 +01:00
control_logic.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
custom_cell_properties.py Add custom cell properties to technologies 2020-01-28 15:46:14 +01:00
delay_chain.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
dff_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff_buf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff_buf_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff_inv.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dff_inv_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
dummy_array.py Bitcell arrays: Create abstract base class 2020-01-28 10:59:58 +01:00
hierarchical_decoder.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
hierarchical_predecode.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
hierarchical_predecode2x4.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
hierarchical_predecode3x8.py Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
module_type.py sram_factory: Give proper priority to overrides 2019-12-19 15:58:00 +01:00
multibank.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
port_address.py Add separate well design rules. 2020-01-23 19:43:41 +00:00
port_data.py Add separate well design rules. 2020-01-23 19:43:41 +00:00
precharge_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
replica_bitcell_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
replica_column.py Add custom cell properties to technologies 2020-01-28 15:46:14 +01:00
sense_amp.py Uncommented tests that use model delays. Fixed issue in sense amp cin. 2019-08-08 18:26:12 -07:00
sense_amp_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
single_level_column_mux_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
tri_gate.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
tri_gate_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
wordline_driver.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
write_driver.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
write_driver_array.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
write_mask_and_array.py Move write mask vias to center to avoid data pins. 2019-12-20 11:48:27 -08:00