OpenRAM/compiler
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
..
base Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
characterizer Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
datasheet Remove line ending whitespace 2022-07-22 19:52:38 +03:00
drc sky130 rba passing :) 2022-09-12 16:07:00 -07:00
gdsMill Add technology parameter for library prefix during uniquification of GDS 2021-07-12 11:01:51 -07:00
model_configs Added shared config which is imported in all model configs. Shared config only hold model type for now. 2021-09-15 13:00:51 -07:00
modules sky130 rba passing :) 2022-09-12 16:07:00 -07:00
router Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
tests add option to keep tmp files when running tests with make 2022-09-08 13:40:48 -07:00
verify add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
Makefile Move tests to test Makefile 2021-11-03 11:36:19 -07:00
debug.py Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
gen_stimulus.py Update copyright year. 2021-01-22 11:23:28 -08:00
globals.py Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
model_data_util.py Remove line ending whitespace 2022-07-22 19:52:38 +03:00
openram.py Use packages for imports. 2022-07-13 15:55:57 -07:00
options.py Remove experimental power option. 2022-05-23 10:08:35 -07:00
printGDS.py Remove line ending whitespace 2022-07-22 19:52:38 +03:00
processGDS.py Remove line ending whitespace 2022-07-22 19:52:38 +03:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Use packages for imports. 2022-07-13 15:55:57 -07:00
uniquifyGDS.py Add technology parameter for library prefix during uniquification of GDS 2021-07-12 11:01:51 -07:00
view_profile.py Update copyright year. 2021-01-22 11:23:28 -08:00