OpenRAM

characterizer

Fixed format test. It was not performing checks due to moving of OPENRAM_HOME. Fixed some tabs and print statements.

2017-04-24 11:55:11 -07:00

gdsMill

Rename unit test files according to test. Modify off-grid pins and blockages. Reorganize router code a bit.

2017-04-12 10:59:04 -07:00

router

Fixed format errors

2017-04-24 13:50:19 -07:00

tests

Fixed format errors

2017-04-24 13:50:19 -07:00

bank.py

Change layer order for add_wire

2016-11-17 14:05:50 -08:00

bitcell_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

bitcell.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

calibre.py

Changed DRC and LVS results output database to end in .db instead of .results. Calibre uses file extensions to determine file type.

2017-04-21 14:07:16 -07:00

contact.py

Merge remote-tracking branch 'bin/clean_unchanged_offset_to_vector'

2016-11-15 10:19:07 -08:00

control_logic.py

Fix error in metal stack

2016-11-17 16:04:01 -08:00

debug.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

design.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

example_config_freepdk45.py

Modified default tech back to freepdk. Config file overrides command line.

2017-01-11 11:47:58 -08:00

example_config_scn3me_subm.py

Modified default tech back to freepdk. Config file overrides command line.

2017-01-11 11:47:58 -08:00

geometry.py

Merge master branch into router

2017-01-09 14:04:37 -08:00

globals.py

Modified default tech back to freepdk. Config file overrides command line.

2017-01-11 11:47:58 -08:00

hierarchical_decoder.py

add rotate_scale function in vector and use it everywhere

2016-11-11 14:33:19 -08:00

hierarchical_predecode2x4.py

merge hierarchical_decoder 2x4 and 3x8 routing functions together

2016-11-22 12:23:55 -08:00

hierarchical_predecode3x8.py

merge hierarchical_decoder 2x4 and 3x8 routing functions together

2016-11-22 12:23:55 -08:00

hierarchical_predecode.py

merge hierarchical_decoder 2x4 and 3x8 routing functions together

2016-11-22 12:23:55 -08:00

hierarchy_layout.py

Created route and add_route for layer assigned wires. It will replace add_wire/wire eventually.

2017-04-19 12:41:13 -07:00

hierarchy_spice.py

Change some debug levels. Fix ngspice test values. ix cwd warning in some tests.

2016-11-15 08:57:06 -08:00

lef.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

logic_effort_dc.py

Change layer order for add_wire

2016-11-17 14:05:50 -08:00

ms_flop_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

ms_flop.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

nand_2.py

add rotate_scale function in vector and use it everywhere

2016-11-11 14:33:19 -08:00

nand_3.py

add rotate_scale function in vector and use it everywhere

2016-11-11 14:33:19 -08:00

nor_2.py

Change layer order for add_wire

2016-11-17 14:05:50 -08:00

openram.py

Modify banner to output temp path

2016-11-15 10:14:04 -08:00

options.py

run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.

2016-11-15 09:03:16 -08:00

path.py

Improve debug messages. Remove add_inst for via in wire.

2016-11-18 14:10:30 -08:00

pinv.py

add rotate_scale function in vector and use it everywhere

2016-11-11 14:33:19 -08:00

precharge_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

precharge.py

add rotate_scale function in vector and use it everywhere

2016-11-11 14:33:19 -08:00

ptx.py

Merge remote-tracking branch 'bin/clean_unchanged_offset_to_vector'

2016-11-15 10:19:07 -08:00

regress.sh

Add regress.sh script for convenience

2016-11-18 08:00:34 -08:00

replica_bitcell.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

replica_bitline.py

Change layer order for add_wire

2016-11-17 14:05:50 -08:00

route.py

Fixed rotated via bug. May still have a via-to-via spacing problem.

2017-04-24 13:47:56 -07:00

sense_amp_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

sense_amp.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

single_level_column_mux_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

single_level_column_mux.py

add rotate_scale function in vector and use it everywhere

2016-11-11 14:33:19 -08:00

sram.py

Change layer order for add_wire

2016-11-17 14:05:50 -08:00

TODO

Add code for isdiff to output diff in tests when files mismatch.

2016-11-12 07:56:50 -08:00

tri_gate_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

tri_gate.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

utils.py

Rename unit test files according to test. Modify off-grid pins and blockages. Reorganize router code a bit.

2017-04-12 10:59:04 -07:00

vector.py

Merge master branch into router

2017-01-09 14:04:37 -08:00

verilog.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

wire.py

Improve debug messages. Remove add_inst for via in wire.

2016-11-18 14:10:30 -08:00

wordline_driver.py

Removed import cell since cell is removed from simplified txt file

2016-11-09 12:20:52 -08:00

write_driver_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

write_driver.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00