Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
d75d17bc8a878c28a88ce0973ce56155e20c419f
OpenRAM/compiler/pgates
T
History
Matt Guthaus 642a5cfe73 Line-wrap pinv debug formatting
2018-07-27 14:07:55 -07:00
..
pbitcell.py
Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.
2018-06-29 11:49:02 -07:00
pgate.py
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
2018-03-23 08:14:09 -07:00
pinv.py
Line-wrap pinv debug formatting
2018-07-27 14:07:55 -07:00
pinvbuf.py
Make pinvbuf have unique names for GDS compliance.
2018-07-26 11:40:40 -07:00
pnand2.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pnand3.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pnor2.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
precharge.py
commiting changes from most recent pull from dev
2018-05-22 17:30:51 -07:00
ptx.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
single_level_column_mux.py
Add enclosing well to column mux. Move well contact to cell boundary.
2018-06-29 11:35:29 -07:00
Powered by Gitea Version: 1.27.2 Page: 123ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API