mirror of https://github.com/VLSIDA/OpenRAM.git
Allow trim netlist to be used for delay and functional simulation. Each class implements a "trim_insts" set of instances that can be removed. By default far left, right, top and bottom cells in the bitcell arrays are kept. Use lvs option in sp_write Fix lvs option in sram. |
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| .. | ||
| __init__.py | ||
| analytical_util.py | ||
| bit_polarity.py | ||
| charutils.py | ||
| delay.py | ||
| elmore.py | ||
| functional.py | ||
| lib.py | ||
| linear_regression.py | ||
| logical_effort.py | ||
| measurements.py | ||
| model_check.py | ||
| neural_network.py | ||
| regression_model.py | ||
| setup_hold.py | ||
| simulation.py | ||
| sram_op.py | ||
| stimuli.py | ||
| trim_spice.py | ||