OpenRAM/compiler/pgates
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
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pand2.py Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
pbuf.py Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
pdriver.py Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
pgate.py Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
pinv.py Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
pinvbuf.py Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
pnand2.py Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
pnand3.py Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
pnor2.py Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
precharge.py Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
ptx.py Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
single_level_column_mux.py Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00