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bank.py
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Added graph creation and functions in base class and lower level modules.
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2019-04-24 14:23:22 -07:00 |
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bank_select.py
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First draft of sram_factory code
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2019-01-16 16:15:38 -08:00 |
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bitcell_array.py
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Added graph creation and functions in base class and lower level modules.
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2019-04-24 14:23:22 -07:00 |
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control_logic.py
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Cleaned up names, added exclusions to narrow paths for analysis.
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2019-04-24 23:51:09 -07:00 |
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delay_chain.py
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Added some comments to the spice files.
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2019-01-25 15:00:00 -08:00 |
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dff.py
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Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.
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2019-05-07 00:52:27 -07:00 |
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dff_array.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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dff_buf.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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dff_buf_array.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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dff_inv.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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dff_inv_array.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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hierarchical_decoder.py
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Added graph creation and functions in base class and lower level modules.
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2019-04-24 14:23:22 -07:00 |
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hierarchical_predecode.py
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First draft of sram_factory code
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2019-01-16 16:15:38 -08:00 |
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hierarchical_predecode2x4.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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hierarchical_predecode3x8.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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multibank.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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precharge_array.py
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Added graph creation and functions in base class and lower level modules.
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2019-04-24 14:23:22 -07:00 |
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replica_bitline.py
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Change pbuf/pinv to pdriver in control logic.
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2019-01-23 12:03:52 -08:00 |
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sense_amp.py
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Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.
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2019-05-07 00:52:27 -07:00 |
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sense_amp_array.py
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Added more accurate bitline delay capacitance estimations
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2019-04-09 01:56:32 -07:00 |
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single_level_column_mux_array.py
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Added more accurate bitline delay capacitance estimations
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2019-04-09 01:56:32 -07:00 |
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tri_gate.py
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Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.
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2019-05-07 00:52:27 -07:00 |
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tri_gate_array.py
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Update unit tests to all use the sram_factory
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2019-03-06 14:12:24 -08:00 |
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wordline_driver.py
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Added linear corner factors in analytical delay model.
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2019-03-04 00:42:18 -08:00 |
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write_driver.py
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Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.
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2019-05-07 00:52:27 -07:00 |
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write_driver_array.py
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Added some comments to the spice files.
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2019-01-25 15:00:00 -08:00 |
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