OpenRAM/compiler
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
..
base Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
characterizer Fix trim spice with new names 2018-10-11 10:36:49 -07:00
gdsMill Add back LEF blockages. Remove "absolute" flags from GDS output 2018-09-05 09:28:43 -07:00
modules Change RBL size to 50% of row size. 2018-10-11 10:39:24 -07:00
pgates Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
router Remove banks from test configs 2018-09-24 11:41:51 -07:00
tests Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
verify Hard code flatten commands for the unique id precharge array 2018-09-13 15:15:41 -07:00
Makefile Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
debug.py Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
example_config_freepdk45.py Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
example_config_scn4m_subm.py Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
gen_stimulus.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
globals.py Rename omits 0 size ports 2018-09-24 13:44:31 -07:00
openram.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
options.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
sram.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
sram_1bank.py Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
sram_2bank.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
sram_4bank.py Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
sram_base.py Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
sram_config.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00