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and2_dec.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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and3_dec.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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and4_dec.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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bank.py
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merge in dev
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2021-05-28 14:06:23 -07:00 |
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bank_select.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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bitcell_array.py
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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bitcell_base_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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col_cap_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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column_mux_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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control_logic.py
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Fix placement of delay chain to align with control logic rows.
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2021-05-05 14:21:53 -07:00 |
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delay_chain.py
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Fix Verilog module typo. Adjust RBL route.
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2021-05-06 14:32:47 -07:00 |
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dff_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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dff_buf.py
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spacing must be two extensions (one for each cell)
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2021-06-04 08:56:06 -07:00 |
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dff_buf_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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dff_inv.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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dff_inv_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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dummy_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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global_bitcell_array.py
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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hierarchical_decoder.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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hierarchical_predecode.py
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56 drc errors on col mux 1port
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2021-05-02 21:49:09 -07:00 |
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hierarchical_predecode2x4.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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hierarchical_predecode3x8.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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hierarchical_predecode4x16.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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local_bitcell_array.py
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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module_type.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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multibank.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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orig_bitcell_array.py
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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port_address.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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port_data.py
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fix port data spare col
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2021-05-04 00:41:20 -07:00 |
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precharge_array.py
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support multi cell wide precharge cells
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2021-04-23 22:49:29 -07:00 |
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replica_bitcell_array.py
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merge in dev
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2021-05-28 14:06:23 -07:00 |
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replica_column.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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row_cap_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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sense_amp_array.py
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use consistent amp spacing
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2021-05-07 11:29:43 -07:00 |
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tri_gate_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wordline_buffer_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wordline_driver_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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write_driver_array.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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write_mask_and_array.py
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Add via when write driver supply is different layer
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2021-04-28 15:16:26 -07:00 |
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