mrg cf63499e76 Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

..

cell_1w_1r.sp

Copy 1rw/1r cell to 1w/1r.

2019-02-24 09:54:45 -08:00

cell_2rw.sp

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

cell_6t.sp

fix custom bitcell labeling; fix gds scaling in labeling

2020-01-15 09:00:02 +00:00

cell_6t.st0

Copy 1rw/1r cell to 1w/1r.

2019-02-24 09:54:45 -08:00

dff.sp

Added scn4m_subm.

2018-09-13 12:53:35 -07:00

dummy_cell_1w_1r.sp

Add other SCMOS dummy cells

2019-07-03 14:28:12 -07:00

dummy_cell_2rw.sp

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

dummy_cell_6t.sp

fix custom bitcell labeling; fix gds scaling in labeling

2020-01-15 09:00:02 +00:00

replica_cell_1w_1r.sp

Copy 1rw/1r cell to 1w/1r.

2019-02-24 09:54:45 -08:00

replica_cell_2rw.sp

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

replica_cell_6t.sp

Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.

2018-11-05 10:59:08 -08:00

sense_amp.sp

Added scn4m_subm.

2018-09-13 12:53:35 -07:00

tri_gate.sp

Added scn4m_subm.

2018-09-13 12:53:35 -07:00

write_driver.sp

Remove unnecessary footer in write driver

2019-08-01 08:59:41 -07:00