mrg cf63499e76 Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

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cell_2rw.gds

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

cell_6t.gds

Remove layer 230 labels from library cells

2018-11-09 11:08:20 -08:00

dff.gds

Flip freepdk45 flop, dff_buf route layer change

2020-06-09 13:48:16 -07:00

dummy_cell_2rw.gds

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

dummy_cell_6t.gds

Add freepdk45 dummy cells

2019-07-03 14:53:44 -07:00

replica_cell_2rw.gds

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

replica_cell_6t.gds

Remove layer 230 labels from library cells

2018-11-09 11:12:31 -08:00

sense_amp.gds

Move output of sense amp to side like other techs

2020-06-26 15:29:27 -07:00

tri_gate.gds

Move sense amp to tri gate routing to M3... not ideal.

2018-04-23 09:14:18 -07:00

write_driver.gds

Move write_driver din left to avoid control signal in spare columns.

2020-07-16 14:47:14 -07:00