mrg cf63499e76 Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

..

base

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

bitcells

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

characterizer

Fix errors in new run_sim calls and corners

2020-11-09 13:59:46 -08:00

custom

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

datasheet

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

drc

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

example_configs

Create single port memory config examples.

2020-11-03 14:42:56 -08:00

gdsMill

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

modules

Add bl/br pins to dummy array

2020-11-12 12:38:09 -08:00

pgates

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Adjust openram options.

2020-11-05 13:12:26 -08:00

sram

Add 200 cycles. Can be commented out or run for shorter.

2020-11-09 15:20:36 -08:00

tests

Add None as sp_file parameter to local_drc_check

2020-11-12 10:01:38 -08:00

verify

Fix missing default path in pex

2020-11-12 14:43:57 -08:00

debug.py

Cleanup imports

2020-11-05 14:32:08 -08:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

Makefile

…

openram.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

options.py

Convert bitcells to 1port and 2port

2020-11-13 08:09:21 -08:00

run_profile.sh

…

sram_factory.py

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00