OpenRAM/compiler
Michael Timothy Grimes ceab1a5daf Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
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base Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
bitcells Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
characterizer Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
datasheet moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
drc Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
gdsMill Fix Future Warning for real 2018-10-10 15:58:16 -07:00
modules Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
pgates Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
router Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
tests Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
verify Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Makefile Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
debug.py Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
example_config_freepdk45.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
example_config_scn4m_subm.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
gen_stimulus.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
globals.py Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
openram.py Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
options.py Fix openram_temp directory 2018-10-06 08:08:01 -07:00
sram.py moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
sram_1bank.py Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
sram_2bank.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
sram_4bank.py Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
sram_base.py Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
sram_config.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00