mrg c472a94f1e Rework bitcells. ... Name them 1port and 2port consistently. Allow cell overrides to cell_1rw and cell_2rw or other. Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.		2020-11-13 10:07:40 -08:00
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cell_1rw.mag	Rework bitcells.	2020-11-13 10:07:40 -08:00
cell_2rw.mag	Rework bitcells.	2020-11-13 10:07:40 -08:00
convertall.sh	Added scn4m_subm.	2018-09-13 12:53:35 -07:00
dff.mag	Added scn4m_subm.	2018-09-13 12:53:35 -07:00
dummy_cell_1rw.mag	Rework bitcells.	2020-11-13 10:07:40 -08:00
dummy_cell_2rw.mag	Rework bitcells.	2020-11-13 10:07:40 -08:00
replica_cell_1rw.mag	Rework bitcells.	2020-11-13 10:07:40 -08:00
replica_cell_2rw.mag	Rework bitcells.	2020-11-13 10:07:40 -08:00
sense_amp.mag	Added scn4m_subm.	2018-09-13 12:53:35 -07:00
tri_gate.mag	Added scn4m_subm.	2018-09-13 12:53:35 -07:00
write_driver.mag	Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver.	2019-08-08 15:49:23 -07:00