mirror of https://github.com/VLSIDA/OpenRAM.git
Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules. |
||
|---|---|---|
| .. | ||
| LICENSE.txt | ||
| SCN3ME_SUBM.30.tech | ||
| __init__.py | ||
| calibreDRC_scn3me_subm.rul | ||
| calibreLVS_scn3me_subm.rul | ||
| tech.py | ||