OpenRAM/compiler/base
Bastian Koppelmann c97bad72db custom_cell_properties: Add bitcell pin name API
this allows users to overrride the pin names to match the names of their
GDS.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2020-02-12 15:37:51 +01:00
..
contact.py Update contact well support. 2020-02-05 18:21:01 +00:00
custom_cell_properties.py custom_cell_properties: Add bitcell pin name API 2020-02-12 15:37:51 +01:00
delay_data.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
design.py Add general well_extend_active DRC in design class. 2020-02-05 18:22:22 +00:00
geometry.py Fix conflicting boundary name 2020-01-24 21:24:44 +00:00
graph_util.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
hierarchy_design.py Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
hierarchy_layout.py tech: Make power_grid configurable 2020-01-28 12:06:34 +01:00
hierarchy_spice.py Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
lef.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
pin_layout.py Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Fix space before comment 2019-06-14 08:43:41 -07:00
utils.py s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
vector.py Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
verilog.py Feedthru port edits. 2019-09-27 14:18:49 -07:00
wire.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_path.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_spice_model.py Move classes to individual file. 2019-07-16 15:18:04 -07:00