OpenRAM/technology/freepdk45/tech
Jesse Cirimelli-Low e7829cf641 allow tech file to specify connection to power rail per net 2026-05-06 10:42:02 -07:00
..
__init__.py Update copyright year 2023-01-28 22:56:27 -08:00
freepdk45.lydrc Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
freepdk45.lylvs By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
freepdk45.lyp Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
freepdk45.lyt Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
scn4m_subm.lyp Add DRC rules and display files 2021-11-22 11:33:27 -08:00
scn4m_subm.lyt Add DRC rules and display files 2021-11-22 11:33:27 -08:00
tech.py allow tech file to specify connection to power rail per net 2026-05-06 10:42:02 -07:00