This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 01:24:39 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
c864427734d46a77def2ec7eca0b9c2e75a75334
OpenRAM
/
technology
/
freepdk45
/
tech
T
History
Jesse Cirimelli-Low
e7829cf641
allow tech file to specify connection to power rail per net
2026-05-06 10:42:02 -07:00
..
__init__.py
Update copyright year
2023-01-28 22:56:27 -08:00
freepdk45.lydrc
Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
2021-11-22 11:33:27 -08:00
freepdk45.lylvs
By default uniquify instances based on macro name.
2022-03-11 18:01:45 -08:00
freepdk45.lyp
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
freepdk45.lyt
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
scn4m_subm.lyp
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
scn4m_subm.lyt
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
tech.py
allow tech file to specify connection to power rail per net
2026-05-06 10:42:02 -07:00
