mrg c472a94f1e Rework bitcells. ... Name them 1port and 2port consistently. Allow cell overrides to cell_1rw and cell_2rw or other. Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.		2020-11-13 10:07:40 -08:00
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__init__.py	Fix space before comment	2019-06-14 08:43:41 -07:00
tech.py	Rework bitcells.	2020-11-13 10:07:40 -08:00