mrg c472a94f1e Rework bitcells. ... Name them 1port and 2port consistently. Allow cell overrides to cell_1rw and cell_2rw or other. Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.		2020-11-13 10:07:40 -08:00
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gds_lib	Rework bitcells.	2020-11-13 10:07:40 -08:00
sp_lib	Rework bitcells.	2020-11-13 10:07:40 -08:00
tech	Rework bitcells.	2020-11-13 10:07:40 -08:00
tf	Add comment layer to display.drf so it is included in .lyp file.	2019-08-27 08:51:34 -07:00
__init__.py	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
layers.map	RELEASE 1.0	2016-11-08 09:57:35 -08:00