| .. |
|
bank.py
|
Connect bank supply rings in sram.py.
|
2018-03-05 13:49:22 -08:00 |
|
bank_select.py
|
Connect bank supply rings in sram.py.
|
2018-03-05 13:49:22 -08:00 |
|
bitcell.py
|
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
|
2018-03-01 23:34:15 -08:00 |
|
bitcell_array.py
|
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
|
2018-03-01 23:34:15 -08:00 |
|
control_logic.py
|
Fixed conflict in delay.py
|
2018-02-27 13:02:22 -08:00 |
|
delay_chain.py
|
Change RBL to allow stages and FO for configuration
|
2018-02-16 11:51:01 -08:00 |
|
dff.py
|
Add dff_buf for buffered flop arrays.
|
2018-03-04 16:13:10 -08:00 |
|
dff_array.py
|
Add dff_buf and dff_array modules.
|
2018-03-23 08:11:51 -07:00 |
|
dff_buf.py
|
Add dff_buf and dff_array modules.
|
2018-03-23 08:11:51 -07:00 |
|
hierarchical_decoder.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
hierarchical_predecode.py
|
Organize top-level files into subdirs.
|
2018-02-09 10:25:24 -08:00 |
|
hierarchical_predecode2x4.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
hierarchical_predecode3x8.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
ms_flop.py
|
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
|
2018-03-01 23:34:15 -08:00 |
|
ms_flop_array.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
precharge.py
|
Fix typo in precharge.
|
2018-02-12 15:34:01 -08:00 |
|
precharge_array.py
|
Change precharge input from clk to en
|
2018-02-12 15:32:47 -08:00 |
|
replica_bitcell.py
|
Organize top-level files into subdirs.
|
2018-02-09 10:25:24 -08:00 |
|
replica_bitline.py
|
RBL width is max of delay chain or bitcell load.
|
2018-03-05 10:23:13 -08:00 |
|
sense_amp.py
|
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
|
2018-03-01 23:34:15 -08:00 |
|
sense_amp_array.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
single_level_column_mux.py
|
Organize top-level files into subdirs.
|
2018-02-09 10:25:24 -08:00 |
|
single_level_column_mux_array.py
|
Organize top-level files into subdirs.
|
2018-02-09 10:25:24 -08:00 |
|
tri_gate.py
|
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
|
2018-03-01 23:34:15 -08:00 |
|
tri_gate_array.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
wordline_driver.py
|
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
|
2018-02-26 16:32:28 -08:00 |
|
write_driver.py
|
Organize top-level files into subdirs.
|
2018-02-09 10:25:24 -08:00 |
|
write_driver_array.py
|
Organize top-level files into subdirs.
|
2018-02-09 10:25:24 -08:00 |
c020d74f26