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bitcell.py
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Error out on single port in sky130
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2020-06-22 15:41:59 -07:00 |
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bitcell_1rw_1r.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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bitcell_1w_1r.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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bitcell_base.py
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Refactor bitcell to bitcell_base. Pep8 format bitcells.
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2019-10-06 01:08:23 +00:00 |
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col_cap_bitcell_1rw_1r.py
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Add option for removing subckt/instances of cells for row/col caps
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2020-06-22 12:35:37 -07:00 |
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dummy_bitcell.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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dummy_bitcell_1rw_1r.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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dummy_bitcell_1w_1r.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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dummy_pbitcell.py
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Add bbox for special DRC rule boundary
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2019-12-05 23:14:25 +00:00 |
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pbitcell.py
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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replica_bitcell.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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replica_bitcell_1rw_1r.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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replica_bitcell_1w_1r.py
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bitcell: Remove hardcoded signal pins
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2020-02-12 15:37:51 +01:00 |
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replica_pbitcell.py
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Add bbox for special DRC rule boundary
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2019-12-05 23:14:25 +00:00 |
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row_cap_bitcell_1rw_1r.py
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Add option for removing subckt/instances of cells for row/col caps
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2020-06-22 12:35:37 -07:00 |
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