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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
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bea6b0b5dcce93e519d207194f96a05ebc679a9f
OpenRAM/compiler/characterizer
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Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test
2018-09-30 22:10:11 -07:00
..
__init__.py
Adding functional test to characterizer and unit tests in both single and multiport
2018-09-20 15:04:59 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Updating functional test. Test can now run a spice simulation and read the dout values from the timing files.
2018-09-28 23:38:48 -07:00
functional.py
updating debug messages in functional test
2018-09-30 22:10:11 -07:00
lib.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
stimuli.py
Updating functional test. Test can now run a spice simulation and read the dout values from the timing files.
2018-09-28 23:38:48 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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