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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 18:48:10 +02:00
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bea07c2319746aa79fd01fac5bb5bde2f868a3c7
OpenRAM/technology/scn4m_subm/gds_lib
T
History
mrg 0fbfa924f7 Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
..
cell_1rw_1r.gds
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
cell_1w_1r.gds
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
cell_6t.gds
Replica bitcell array working
2019-06-19 16:03:21 -07:00
dff.gds
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
dummy_cell_1rw_1r.gds
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
dummy_cell_1w_1r.gds
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
dummy_cell_6t.gds
Replica bitcell array working
2019-06-19 16:03:21 -07:00
replica_cell_1rw_1r.gds
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
replica_cell_1w_1r.gds
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
replica_cell_6t.gds
Replica bitcell array working
2019-06-19 16:03:21 -07:00
sense_amp.gds
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.gds
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.gds
Well contact cleanup for SCMOS TSMC 0.35
2019-04-26 10:19:11 -07:00
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