Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.

2018-03-23 08:13:20 -07:00

..

bank_select.py

Single bank passing DRC and LVS again.

2018-03-23 08:13:10 -07:00

bank.py

Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.

2018-03-23 08:13:20 -07:00

bitcell_array.py

Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.

2018-03-23 08:12:47 -07:00

bitcell.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

control_logic.py

Single bank passing DRC and LVS again.

2018-03-23 08:13:10 -07:00

delay_chain.py

Recreate delay chain and RBL to have vertical poly only.

2018-03-23 08:12:47 -07:00

dff_array.py

Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.

2018-03-23 08:12:47 -07:00

dff_buf_array.py

Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.

2018-03-23 08:12:47 -07:00

dff_buf.py

Add dff_buf and dff_array modules.

2018-03-23 08:11:51 -07:00

dff.py

Add dff_buf for buffered flop arrays.

2018-03-04 16:13:10 -08:00

hierarchical_decoder.py

Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.

2018-03-23 08:13:20 -07:00

hierarchical_predecode2x4.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode3x8.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode.py

Single bank passing DRC and LVS again.

2018-03-23 08:13:10 -07:00

ms_flop_array.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

ms_flop.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

precharge_array.py

Change precharge input from clk to en

2018-02-12 15:32:47 -08:00

precharge.py

Fix typo in precharge.

2018-02-12 15:34:01 -08:00

replica_bitcell.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

replica_bitline.py

Move label pins to center like layout pins.

2018-03-23 08:12:59 -07:00

sense_amp_array.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.

2018-03-23 08:13:20 -07:00

single_level_column_mux.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

tri_gate_array.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.

2018-03-23 08:13:20 -07:00

write_driver_array.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00