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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 17:39:02 +02:00
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b9bb6898af60007b048149cd02bac1706572d9ab
OpenRAM
/
technology
/
freepdk45
/
tech
T
History
Vikash Patel
b9bb6898af
Fix for Missing lef_rom_interconnect in tech.py
2025-10-17 14:40:03 +05:30
..
__init__.py
Update copyright year
2023-01-28 22:56:27 -08:00
freepdk45.lydrc
Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
2021-11-22 11:33:27 -08:00
freepdk45.lylvs
By default uniquify instances based on macro name.
2022-03-11 18:01:45 -08:00
freepdk45.lyp
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
freepdk45.lyt
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
scn4m_subm.lyp
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
scn4m_subm.lyt
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
tech.py
Fix for Missing lef_rom_interconnect in tech.py
2025-10-17 14:40:03 +05:30
