Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates.		2018-11-28 12:42:29 -08:00
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pand2.py	pgate inputs and outputs are all on M1 for flexible via placement when using gates.	2018-11-28 12:42:29 -08:00
pbuf.py	pgate inputs and outputs are all on M1 for flexible via placement when using gates.	2018-11-28 12:42:29 -08:00
pgate.py	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00
pinv.py	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00
pinvbuf.py	Add copy power pin function	2018-10-08 09:56:39 -07:00
pnand2.py	Add netlist only mode to new pgates	2018-11-26 15:29:42 -08:00
pnand3.py	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00
pnor2.py	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00
precharge.py	Change en to en_bar in precharge. Fix logic for inverted p_en_bar.	2018-11-27 14:17:55 -08:00
ptx.py	Limit ps, pd, as, ad precision in ptx.	2018-11-28 09:47:54 -08:00
single_level_column_mux.py	Merge branch 'dev' into multiport_layout	2018-11-08 18:00:28 -08:00