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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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b1f3bd97e5c49129474bd672b1d5899d580135e7
OpenRAM/compiler/router
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Matt Guthaus 88f43cc754 Add the minimum pin enclosure that has DRC correct pin connections.
2018-10-24 16:41:33 -07:00
..
tests
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direction.py
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grid_cell.py
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grid_path.py
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grid_utils.py
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grid.py
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router.py
Add the minimum pin enclosure that has DRC correct pin connections.
2018-10-24 16:41:33 -07:00
signal_grid.py
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signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
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supply_router.py
Add the minimum pin enclosure that has DRC correct pin connections.
2018-10-24 16:41:33 -07:00
vector3d.py
…
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