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luke
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OpenRAM
mirror of
https://github.com/VLSIDA/OpenRAM.git
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b00fc040a3
OpenRAM
/
technology
/
freepdk45
History
Hunter Nichols
b00fc040a3
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
..
gds_lib
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sp_lib
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
tech
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
tf
Add display techfiles from NCSU PDKs.
2018-03-02 10:30:03 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00