Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell.		2018-10-17 07:28:56 -07:00
..
pbitcell.py	adding 6T transistor size parameters to tech files for use in pbitcell.	2018-10-17 07:28:56 -07:00
pgate.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pinv.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
pinvbuf.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pnand2.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
pnand3.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
pnor2.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
precharge.py	Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell.	2018-10-16 06:57:53 -07:00
ptx.py	Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check.	2018-09-12 01:53:41 -07:00
single_level_column_mux.py	Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.	2018-09-09 22:06:29 -07:00