Matt Guthaus a8e1abdce8 Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge.

2018-02-05 11:36:46 -08:00

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characterizer

Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge.

2018-02-05 11:36:46 -08:00

gdsMill

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router

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tests

Update new LEF files for unit tests.

2018-02-05 10:27:56 -08:00

verify

Specify file format for sp spice extension.

2018-02-02 15:33:35 -08:00

bank.py

Ensure wells are spaced in the bank select and column decoder

2018-02-02 15:26:15 -08:00

bitcell_array.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-01-31 17:37:16 -08:00

bitcell.py

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contact.py

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control_logic.py

Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working.

2018-02-05 10:22:38 -08:00

debug.py

Clean up messages.

2018-01-31 11:54:20 -08:00

delay_chain.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

design.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

example_config_freepdk45.py

Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations.

2018-02-02 19:33:07 -08:00

example_config_scn3me_subm.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

geometry.py

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globals.py

Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations.

2018-02-02 19:33:07 -08:00

hierarchical_decoder.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

hierarchical_predecode2x4.py

Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.

2018-02-02 14:08:56 -08:00

hierarchical_predecode3x8.py

Fix input discrepencies in pre3x8

2018-01-29 15:25:41 -08:00

hierarchical_predecode.py

Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.

2018-02-02 14:08:56 -08:00

hierarchy_layout.py

Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working.

2018-02-05 10:22:38 -08:00

hierarchy_spice.py

Remove level of indirection to ptx devices to allow LVS symmetries.

2018-01-29 15:25:15 -08:00

lef.py

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Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

ms_flop_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

ms_flop.py

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openram.py

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

options.py

Add -d option to not delete temp directory on successful runs.

2018-02-01 11:53:02 -08:00

path.py

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pgate.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

pin_layout.py

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pinv.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

pnand2.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

pnand3.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

pnor2.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

precharge_array.py

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precharge.py

Fix precharge nwell contact spacing DRC violatin.

2018-01-26 13:53:45 -08:00

ptx.py

Remove level of indirection to ptx devices to allow LVS symmetries.

2018-01-29 15:25:00 -08:00

regress.sh

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replica_bitcell.py

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replica_bitline.py

Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working.

2018-02-05 10:22:38 -08:00

route.py

Fix gnd connection in control logic.

2018-02-02 13:04:38 -08:00

sense_amp_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

sense_amp.py

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single_level_column_mux_array.py

Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.

2018-02-02 15:17:21 -08:00

single_level_column_mux.py

Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.

2018-02-02 15:17:21 -08:00

sram.py

Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations.

2018-02-02 19:33:07 -08:00

tri_gate_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

tri_gate.py

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utils.py

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vector.py

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verilog.py

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wire.py

Fix gnd connection in control logic.

2018-02-02 13:04:38 -08:00

wordline_driver.py

Fix nand input ordering to correct netgen LVS error of wordline driver.

2018-01-29 15:36:37 -08:00

write_driver_array.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-01-31 17:37:16 -08:00

write_driver.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-01-31 17:37:16 -08:00