| .. |
|
and2_dec.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
and3_dec.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
and4_dec.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
bank.py
|
offset bank coordinates
|
2021-05-03 15:51:53 -07:00 |
|
bank_select.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
bitcell_array.py
|
Reimplement trim options (except on unit tests).
|
2021-04-07 16:07:56 -07:00 |
|
bitcell_base_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
col_cap_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
column_mux_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
control_logic.py
|
Add wells to driver stages. Remove unnecessary height/center in control logic.
|
2021-03-25 10:00:24 -07:00 |
|
delay_chain.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_buf.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_buf_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_inv.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_inv_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dummy_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
global_bitcell_array.py
|
Add custom parameter for wordline layer
|
2021-04-21 11:04:01 -07:00 |
|
hierarchical_decoder.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
hierarchical_predecode.py
|
56 drc errors on col mux 1port
|
2021-05-02 21:49:09 -07:00 |
|
hierarchical_predecode2x4.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
hierarchical_predecode3x8.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
hierarchical_predecode4x16.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
local_bitcell_array.py
|
Abstracted LEF added. Params for array wordline layers.
|
2021-04-22 09:44:25 -07:00 |
|
module_type.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
multibank.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
orig_bitcell_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
port_address.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
port_data.py
|
fixed port_data typo
|
2021-05-03 14:39:51 -07:00 |
|
precharge_array.py
|
support multi cell wide precharge cells
|
2021-04-23 22:49:29 -07:00 |
|
replica_bitcell_array.py
|
support multi cell wide precharge cells
|
2021-04-23 22:49:29 -07:00 |
|
replica_column.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
row_cap_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
sense_amp_array.py
|
56 drc errors on col mux 1port
|
2021-05-02 21:49:09 -07:00 |
|
tri_gate_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
wordline_buffer_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
wordline_driver_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
write_driver_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
write_mask_and_array.py
|
Add via when write driver supply is different layer
|
2021-04-28 15:16:26 -07:00 |
14e087a5eb