OpenRAM/compiler/bitcells
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
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bitcell.py Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
bitcell_1rw_1r.py Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
bitcell_1w_1r.py Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
pbitcell.py Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
replica_bitcell.py First draft of sram_factory code 2019-01-16 16:15:38 -08:00
replica_bitcell_1rw_1r.py First draft of sram_factory code 2019-01-16 16:15:38 -08:00
replica_bitcell_1w_1r.py Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
replica_pbitcell.py First draft of sram_factory code 2019-01-16 16:15:38 -08:00