OpenRAM/compiler/base
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
..
contact.py Add npc enclosure to poly contacts 2020-06-11 11:53:59 -07:00
custom_cell_properties.py sense_amp: Allow custom pin names 2020-02-17 15:20:12 +01:00
delay_data.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
design.py Fix precharge offset. Move well rules to design class. 2020-06-09 15:28:50 -07:00
errors.py Add exception errors file 2020-04-08 16:55:45 -07:00
geometry.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
graph_util.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
hierarchy_design.py DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
hierarchy_layout.py Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
hierarchy_spice.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
lef.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
pin_layout.py Add pin and label purposes 2020-06-11 11:54:51 -07:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Fix space before comment 2019-06-14 08:43:41 -07:00
utils.py s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
vector.py Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
verilog.py Feedthru port edits. 2019-09-27 14:18:49 -07:00
wire.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
wire_path.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
wire_spice_model.py Move classes to individual file. 2019-07-16 15:18:04 -07:00