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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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a27cdb4fbc1e157b6e7f2fe7302239545d14cac2
OpenRAM/compiler/base
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Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies.
2018-10-15 06:29:51 -07:00
..
contact.py
Remove unique id in contact that was used for debugging
2018-09-04 16:40:52 -07:00
design.py
Redesign of pbitcell for newer process technolgies.
2018-10-15 06:29:51 -07:00
geometry.py
Add back LEF blockages. Remove "absolute" flags from GDS output
2018-09-05 09:28:43 -07:00
hierarchy_design.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_layout.py
Comment debug for possible performance issue
2018-09-24 11:44:32 -07:00
hierarchy_spice.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
lef.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
Add inflate blockages and remove pins from blockages.
2018-09-05 11:06:17 -07:00
route.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
utils.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
vector.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
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