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base
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Add conditional power pins to Verilog model.
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2021-04-30 14:15:32 -07:00 |
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bitcells
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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characterizer
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Removed measurement check which conflicts with multiport memories
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2021-04-21 15:53:27 -07:00 |
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custom
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Add noninverting logic function to custom decoder cells.
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2021-04-22 16:13:54 -07:00 |
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datasheet
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Merge branch 'dev' into automated_analytical_model
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2021-02-01 01:49:45 -08:00 |
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drc
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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example_configs
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Add vdd/gnd pins to the side.
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2021-05-03 15:14:15 -07:00 |
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gdsMill
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Make default no magnification to text. PEP8 Cleanup
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2020-12-09 11:42:28 -08:00 |
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modules
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Add via when write driver supply is different layer
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2021-04-28 15:16:26 -07:00 |
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pgates
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Add wells to driver stages. Remove unnecessary height/center in control logic.
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2021-03-25 10:00:24 -07:00 |
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router
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Add vdd/gnd pins to the side.
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2021-05-03 15:14:15 -07:00 |
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sram
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Add vdd/gnd pins to the side.
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2021-05-03 15:14:15 -07:00 |
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tests
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Update unit test results with new Verilog models.
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2021-04-15 15:48:20 -07:00 |
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verify
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Remove option that causes errors and is unused.
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2021-03-01 16:36:27 -08:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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gen_stimulus.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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globals.py
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Specify ImportError to see other errors
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2021-04-22 16:13:32 -07:00 |
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openram.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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options.py
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Abstracted LEF added. Params for array wordline layers.
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2021-04-21 11:04:01 -07:00 |
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printGDS.py
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Add printGDS script to aid debugging things.
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2020-12-02 11:52:38 -08:00 |
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processGDS.py
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Make default no magnification to text. PEP8 Cleanup
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2020-12-09 11:42:28 -08:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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view_profile.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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