Matt Guthaus 9ecfaf16ea Add the factory class

2019-01-16 17:04:28 -08:00

..

base

Add the factory class

2019-01-16 17:04:28 -08:00

bitcells

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

characterizer

falling_edge not negative_edge

2019-01-11 15:17:27 -08:00

datasheet

removed openram placeholder logo to stage for public push

2019-01-09 12:32:17 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

example_configs

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

gdsMill

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

modules

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

pgates

Convert all contacts to use the sram_factory

2019-01-16 16:56:06 -08:00

router

Added router timing code. Commented combine adjacent pins due to run-time complexity

2018-12-07 13:54:18 -08:00

tests

Add the factory class

2019-01-16 17:04:28 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

git_id

track git_id

2018-12-05 16:13:52 -08:00

globals.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

options.py

Convert all contacts to use the sram_factory

2019-01-16 16:56:06 -08:00

profile_stats.py

Add profile scripts

2018-12-07 08:56:40 -08:00

run_profile.sh

Add profile scripts

2018-12-07 08:56:40 -08:00

sram_1bank.py

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_base.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

sram_config.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

sram.py

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

view_profile.py

Add profile scripts

2018-12-07 08:56:40 -08:00