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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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9744bc516ac1d14d5142f2c0607deb4b2eed331a
OpenRAM
/
technology
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scn4m_subm
/
sp_lib
T
History
Hunter Nichols
9321f0461b
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
..
cell_1rw_1r.sp
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
cell_6t.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
dff.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
replica_cell_1rw_1r.sp
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
replica_cell_6t.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sense_amp.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
