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luke
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OpenRAM
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8e890c2014476ad26bf97d2605841888051383a7
OpenRAM
/
compiler
/
example_configs
T
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mrg
b7c43ae674
Fix 1w/1r example
2020-07-23 14:17:13 -07:00
..
big_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_1rw_1r_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_1rw_2mux_scn4m_subm.py
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
example_config_1w_1r_scn4m_subm.py
Fix 1w/1r example
2020-07-23 14:17:13 -07:00
example_config_freepdk45.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_scn4m_subm.py
revert example scn4m to non netlist only
2020-02-09 23:52:11 -08:00
giant_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
medium_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00